1. Field of the Invention
The invention relates to the field of semiconductor device fabrication techniques and structures and more particularly to the field of fabrication techniques for the fabrication of very large scale integrated circuits (VLSI) having increased density and reliability and containing FET devices, polysilicon and diffused N+ interconnect lines with self-aligned gates for such devices and self-aligned contacts for such devices and lines, and metalized interconnect lines, said lines interfacing variously with the contacts to the devices and the polysilicon and N+ diffused lines to provide VLSI circuits of increased density and reliability.
2. Prior Art
The semiconductor art has been concerned with reducing the size and power consumption of individual devices and integrated circuits in order to increase the logic power of these circuits per unit area. A particular effort has been extended in the area of monolithic random access memories (RAM's) and read only memories (ROM's) having very large memory capacity. Many things have been done over the years in an attempt to reduce the size of devices and improve tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required for the fabrication of the individual FET devices used in these integrated circuits. However, because of alignment tolerances, the FET devices must be designed with larger geometry than they would have to be if perfect mask alignment were obtained. Furthermore, becaues of alignment tolerances, the FET devices must be spaced further apart than otherwise necessary in order to allow for the misalignment in the formation of such devices and electrical contacts thereto, and of the interconnection lines and their associated contact positions. Consequently, there is a need for improved integrated circuit fabrication techniques for producing VLSI cir-cuits including FET devices and conducting lines having reduced sensitivity to mask alignment thereby to afford increased density and reliability.